The semiconductor wafer fabrication process is an amazing feat of physics and engineering, involving thousands of minute steps that build upon one another to create devices that are integral to the modern world. At each stage in the process, varying sets of tools perform operations that physically alter the surface of wafers to achieve desired layer profiles. Due to the complexity of the entire process, it is imperative that tools are calibrated with optimized recipes to minimize defects and maximize product yield.
By high-volume production, much of the low-hanging issues have been resolved and the onus is placed squarely upon product engineers to further refine the process by weeding out more subtle defects. These defect signatures will often resemble the physical structure or movement patterns of the process tools and have low failure rates (<500ppm), hidden beneath process variation and mountains of test fail data. Using the methodology outlined in this paper, demonstrable success was achieved in uncovering obscured wafer defect signatures, leading to failure analysis and corrective action enacted by the foundry.
