Video was recorded in March 2025 using JMP 18.
Are you looking for ways to determine an effective way to trade off power and speed to find a sweet spot for your semiconductor chip design? Are you an engineer responsible for designing or doing validation testing to assure that your hardware solutions satisfy the requirements or your customers? Do you seek efficient ways to predict the behavior of a system-on-a-chip (SOC) under real conditions?
In this Mastering JMP session, we use DOE and JMP Pro predictive modeling to design and evaluate expected performance for a CMOS semiconductor SOC. We will:
- Develop a high-quality timing and power model to predict system behavior to ensure that it meets specifications.
- Correlate circuit simulation results to silicon characterization measurements to validate the circuit design
- Determine optimal SOC operating conditions to achieve desired performance targets.
