In semicondutor industry, VMIN and IDDQ (leakage) are very critical parameters for mobile CPU power and performance. For each device, there will be a pair of VMIN and IDDQ for each power domain, such as logic and memory. There is certain degree of correlation between VMIN and IDDQ (device with higher VMIN tends to have smaller IDDQ) as shown below (gree circles represent 95% of the population):
Let us assume the left bivariat chat corresponds to logic IDDQ (X-axis) vs VMIN (Y-axis) while the right one corresponds to memory. If someone were to compare VMIN vs IDDQ variation between logic and memory, how would you go about and do so?
Thanks!